Low-Power 8-Bit Pipelined Adc with Current Mode Mdac (Paperback)

In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying digital-to-analog converter (MDAC). The main focus is to design and optimize the MDAC. We design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages consisting of Sample-and-Hold, 1.5-bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2-bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in Verilog-A and MATLAB. A first order digital error-correction algorithm is implemented in MATLAB. The design is simulated in UMC 0.18μm technology in Cadence environment.

Low-Power 8-Bit Pipelined Adc with Current Mode Mdac (Paperback)

Specifications

Language: English
Publisher: KS Omniscriptum Publishing
Book Format: Paperback
Original Languages: English
Number of Pages: 76
Author: Khurram Shahzad
Title: Low-Power 8-Bit Pipelined Adc with Current Mode Mdac
ISBN-13: 9783843370264
Publication Date: November, 2010
Assembled Product Dimensions (L x W x H): 6.00 x 0.18 x 9.00 Inches
ISBN-10: 3843370265